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Lattice Semiconductor
Functional Description
When the frame experiences excessive collision or late collision, the statistics bit for the appropriate condition is set
and the tx_discfrm signal is asserted. This indicates an error condition.
Internal Data Buffer and FIFO Interfaces
In the Classic TSMAC IP core and SGMII Easy Connect option, the transmit and receive sections each contain
internal FIFO buffers. In the Gigabit MAC option, only the Rx internal FIFO buffer is used. Note that External Trans-
mit and Receive FIFOs (that interface to the MAC client side) are still required to store variable-length normal pack-
ets.
On the receive side, the internal FIFO buffer is used to support the dropping of packets less than 64 bytes and to
provide additional data buffering for normal packets. The core provides a feature where the user can block all the
frames that are shorter than the minimum frame length of 64 bytes in the TSMAC IP core itself (for example colli-
sion fragments, runt frames, and such). This prevents these frames from reaching the user's application.
On the transmit side, the internal FIFO buffer stores the first 64 bytes of the frame. This ensures that the TSMAC IP
core can re-transmit the frame automatically without help from the application software during an in-window colli-
sion. This important feature prevents the propagation of collision information into the application software.
The TSMAC IP core provides two independent interfaces for use with external Transmit and Receive FIFOs. This
feature enables the TSMAC IP core to support full duplex operation in either 10/100 or 1G modes.
G/MII Interface
The G/MII module uses the clock supplied by the external PHY. The core implements the standard G/MII interface
to connect to the PCS layer.
The module implementing the interface also converts the data to a format usable by the MAC. In the 1G mode, the
8-bit data at the interface is presented to the 8-bit data path of the MAC. In the 10/100 mode, the 4-bit MII data is
packed and input to the 8-bit data path of the MAC.
Although not implemented as a separate module, the Reconciliation Sub-layer is implemented as a part of the
G/MII interface. This module is responsible for passing the data from one clock domain (TSMAC IP core) to the
other G/MII.
(Optional) Media Independent Interface Management Module (MIIM)
The MIIM accesses management information from the PHY device and writes to or reads from the PHY registers.
A single MIIM can address up to 32 PHY devices. This module runs off its own clock called mdc. The standard
specifies this clock to be at 2.5MHz, but PHY devices can accept a 10MHz mdc clock. Therefore, the TSMAC IP
core can have a MIIM that is capable of running at up to 10MHz.
The MIIM read or write operations are specified in the GMII_MNG_CTL register. This register also specifies the
addressed PHY and the register within the PHY that needs to be accessed. The Command Finished bit in the
GMII_MNG_CTL register is reset as soon as a command to read or write is given. It is set only when the MIIM
module completes the operation. While the interface is busy, the GMII_MNG_CTL register cannot be overwritten,
and all write operations to the register are ignored. For a write operation, the data to be written is stored in the
GMII_MNG_DAT register. For a read operation, the data read from the addressed PHY is stored in this register.
The ready bit in the GMII_MNG_CTL is set at the end of the read/write operation.
IPUG51_03.0, December 2010
24
Tri-Speed Ethernet MAC User’s Guide
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